The present invention relates to clocked electronic circuits and more particularly to a clock buffer circuit that includes an LC circuit to reduce jitter in the clock circuit output frequency.
In computer systems, networking equipment, and numerous other types of electronic equipment, system clocks are commonly used. The system clocks are often buffered and distributed throughout the system for use by processors, memories, DMA controllers, arbitration logic, and many other components, boards and systems that require an accurate frequency. To provide adequate fan-out from the source of the system clock, several stages of buffers are often used. It is well known that such buffer stages can introduce undesirable jitter into the clock signal. The jitter can result from clock transitions that occur sooner or later than normally expected. While jitter can occur for a number of reasons, it is understood that variations in the power supply voltage can result in clock litter.
Problems associated with jitter become worse as the clock frequencies that are employed increase. Moreover, with faster circuits, cycle times are reduced. The reduction in cycle times often mandates reductions in jitter specifications to achieve reliable operation.
Currently, when it is necessary to provide a clock with very low jitter characteristics, a phase locked loop (PLL) is employed. PLLs, however, tend to be complex, costly, and require substantial board area for the components necessary to implement the PLL. In view of the space and cost considerations associated with the use of PLLs to reduce clock jitter, their use is often limited.
Accordingly, it would be desirable to have a low cost and reliable jitter reduction clock buffer circuit that may be fabricated on an integrated circuit and used throughout clocked electronic devices.
A circuit and method for reducing clock jitter at the output of a clock buffer is disclosed. The clock buffer includes an input stage amplifier and a buffer stage. In a preferred embodiment, the input stage amplifier comprises a differential amplifier that receives differential inputs from a clock source. The differential amplifier is coupled to an input of the buffer stage. The buffer stage has an output that comprises the clock buffer output. The buffer stage output is coupled to the clocked load. The buffer stage output is also coupled to an LC circuit. More specifically, an inductor and a capacitor are coupled between the buffer stage output and a ground node of the clock buffer. The values of the inductor and capacitor are specified so as to create a resonant circuit having a resonant frequency equal to the desired clock frequency. The LC circuit acts as a bandpass filter and reduces the frequency components away from the desired frequency of operation.
In a preferred embodiment, the inductor and the capacitor forming the LC resonant circuit are fabricated in silicon along with the clock buffer. Alternatively, either one or both of the components may be discrete or off chip components that are coupled to the clock buffer output.
Additionally, to permit tuning of the resonant LC circuit to the desired clock frequency, plural capacitors and/or inductors may be fabricated on-chip and selected capacitors and/or inductors coupled between the clock buffer output and ground to achieve the desired bandpass frequency. The capacitors and/or inductors may have interconnects to the clock buffer output made external to the chip or alternatively, via semiconductor switches that are located on-chip but controlled via external control signals.
Other features, aspects and advantages of the presently disclosed clock buffer circuit for reducing clock jitter will be apparent from the Detailed Description of the Invention that follows.